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Schematic of DRO with cascade structure

Digitally-controlled ring oscillator for wide tuning range applications

Shirin Askari, Mohsen Saneei


In this paper, two digitally-controlled ring oscillators (DROs) with similar structure but different constructive cells have been proposed. These proposed DROs include of 5 stages, and each stage contains 10 parallel delay cells. In addition, each stage has fine and coarse parts for adjusting the output frequency. The proposed designs have a wide frequency range and high frequency. The frequency range of the first DRO changes from 1.566 to 20.25 GHz (92.6%) and for the second DRO, its frequency is from 2.218 to 22.86 GHz (90.31%). By considering all possible digital codes for fine and coarse stages, the power consumption of the first DRO changes from 1.1 to 13.64 mW, while this value for the second DRO varies from 144.1 μW to 1.76 mW. The phase noise of the first DRO at the center frequency of 20.25 GHz and the 1 MHz offset is equal to –76.24 dBc/Hz, and at 10 MHz offset the phase noise is equal to –104 dBc/Hz. The phase noise of the second DRO at the center frequency of 22.86 GHz and the 1 MHz offset is equal to –66.64 dBc/Hz, and at the 10 MHz offset the phase noise is equal to –95.39 dBc/Hz. The proposed DROs have been simulated by using the Cadence software in TSMC 65nm CMOS technology and 1.2 V power supply.


DRO; digitally-controlled ring oscillator; wide frequency range; high frequency

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