Low-energy 3:2 compressor using XOR-XNOR gate combined with 2:1 multiplexer in QCA technology

Sankit Kassa; Neeraj Kumar Misra; Seyed-Sajad Ahmadpour; Bandan Kumar Bhoi

doi:10.3103/S0735272724030014

Authors

Sankit Kassa Symbiosis International Deemed University, Pune, India https://orcid.org/0000-0002-8714-2073
Neeraj Kumar Misra VIT-AP University, Amaravathi, India https://orcid.org/0000-0002-7907-0276
Seyed-Sajad Ahmadpour Kadir Has University, Istanbul, Turkey https://orcid.org/0000-0003-2462-8030
Bandan Kumar Bhoi Veer Surendra Sai University of Technology, Burla, India https://orcid.org/0000-0003-2916-2903

DOI:

https://doi.org/10.3103/S0735272724030014

Keywords:

low power, QCA, Nanotechnology, Digital logic, Digital design, nanocomputing, binary compressor

Abstract

In the field of circuit design, there is a growing trend toward the design of high-speed circuits with a minimum amount of faults on a nanoscale level. In this way, quantum-dot cellular automata (QCA) is a nanoscale-based paradigm that uses a quantum cell with four dots and two electrons to compute logic bits, comparable to transistor-based CMOS architecture. This article focuses on the low-energy compressor design employing an XOR-XNOR gate and a 2:1 multiplexer. Furthermore, a compressor design provides 152 cells employing a coplanar arrangement in QCA with eight majority gates (MG). The compressor energy dissipation is examined using the QCAPro tool, which has various tunneling energy values. Furthermore, the compressor thermal and polarisation layouts are presented. The novel circuit performance is compared with the best existing circuits on QCA regarding cell count, entire area, MG, and latency to assess the newly designed compressor performance. The proposed compressor is tested using the missing cells in the QCADesigner tool. This design has only 5 test vectors, 100% fault coverage, and is best suited for design for testability (DFT). The proposed compressor can be used with various multipliers, including the Wallace tree multiplier, DADDA multiplier, and higher order 7:3 compressor.

Author Biographies

Sankit Kassa, Symbiosis International Deemed University, Pune

I am an Assistant Professor at Department of Electronics and Telecommunication Engineering in Symbiosis Institute of Technology, Symbiosis International (Deemed University).

Neeraj Kumar Misra, VIT-AP University, Amaravathi

I am working as Associate Professor at VIT-AP University

Seyed-Sajad Ahmadpour, Kadir Has University, Istanbul

I am currently working at the Department of Computer Engineering. Faculty of Engineering and Natural Sciences, Kadir Has University, Istanbul, Türkiye.

Bandan Kumar Bhoi, Veer Surendra Sai University of Technology, Burla

I am working as Assistant Professor at Department of Electronics and Telecommunication, Veer Surendra Sai University of Technology: Burla, Orissa, IN

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