Low-power 8T memory cell of register file for 180 nm technology

O. M. Grudanov

doi:10.3103/S0735272723100059

Authors

O. M. Grudanov National Aviation University, Kyiv, Ukraine

DOI:

https://doi.org/10.3103/S0735272723100059

Keywords:

SRAM, RFSRAM, low-power memory, butterfly curves, static-noise margin, SNM

Abstract

This paper proposes a method of definition of transistor dimensions for an 8-transistor (8T) cell of a resister file static memory RFSRAM (register file static random access memory) for development of low-power dual-port register files and dual-port SRAM (static random access memory) for power consumption decrease. This method can also be used for 6-transistor (6T) cells of single-port static RAM. The method is based on the analysis of so-called butterfly curves (BC) and the search for such values of transistor dimensions and their threshold voltage dispersion, providing for a given critical minimum supply voltage and the existence of one intersection and one contact of the BC. We compare the obtained characteristics of silicon memory samples and their critical voltage with the simulation results in the reading and writing modes dependent on the supply voltage. Experimental samples of memory cells manufactured at the TSMC factory using 180 nm have technology passed testing at 0.75–1.8 V.

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