Analysis of complex linear periodically time-varying circuits by method of reduced matrix D-trees

Authors

  • Yuriy Shapovalov Lviv Polytechnic National University, Lviv, Ukraine
  • Dariya Bachyk Lviv Polytechnic National University, Lviv, Ukraine https://orcid.org/0000-0002-0535-0398
  • Ksenia Detsyk Lviv Polytechnic National University, Lviv, Ukraine
  • Roman Romaniuk Lviv Polytechnic National University, Lviv, Ukraine https://orcid.org/0009-0007-3541-6531
  • Ivan Shapovalov Queen’s University, Kingston, Canada

DOI:

https://doi.org/10.3103/S0735272723060018

Keywords:

periodically time-varying circuits, frequency symbolic method, FSM, periodically time-varying matrix model, d-tree method, matrix d-tree method

Abstract

The paper proposes the method of reduced matrix D-trees, which is an improved version of the method of matrix d-trees. This method is a further development of the application of one of the subcircuit methods, the so-called d-tree method, to the symbolic analysis of linear circuits with constant parameters The method of reduced matrix D-trees, like the d-tree method, provides a significant reduction in the required computer time for modeling circuits, which has a mathematical meaning, consisting in the bringing out of similar terms in the formed complex symbolic expressions. Since there are, in fact, many symbolic terms in such expressions, this reduction in time is due to such factoring. The method is illustrated using a model of a long line consisting of a cascade connection of a large number of elementary links. The results of the computer simulation are also presented.

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General view of output signal for different m for steady-state mode of MAOPCs system

Published

2023-04-27

Issue

Section

Research Articles