Structural and parametric optimization of bandgap voltage reference

L. N. Pavlov; Denys Lebedev

doi:10.3103/S0735272722070056

Authors

L. N. Pavlov National Technical University of Ukraine “Igor Sikorsky Kyiv Polytechnic Institute”, Ukraine https://orcid.org/0000-0001-8273-9607
Denys Lebedev National Technical University of Ukraine “Igor Sikorsky Kyiv Polytechnic Institute”, Ukraine https://orcid.org/0000-0001-8672-8366

DOI:

https://doi.org/10.3103/S0735272722070056

Abstract

The article shows the possibility of reducing the temperature coefficient for the bandgap voltage reference (BVR) built on bipolar transistors. To do this, as the first step, it is proposed to divide the temperature range of BVR operation into two intervals. Since the most probable working interval corresponds to the range of positive temperatures, such division makes it possible to halve the temperature coefficient for the most probable working area on condition of an appropriate BVR adjustment. The introduction of weights for BVR optimization involves giving preference to the working interval of positive temperatures. It provides a direction of search for the optimal solution when formalizing the optimization process. The second step involves the proposal of a functional block diagram with compensators of the decline of temperature characteristic. The paper also proposes electric circuits of a typical compensator and the circuits for connecting one and two compensators to uncompensated BVR. This also determines the rule of introducing further compensators, if expedient. The parametric optimization of the proposed BVR circuits and the experimental study of BVR circuit with one compensation link have been performed. The above optimization resulted in a reduced value of temperature coefficient at the level of 2.88 ppm/°C for the circuit with one compensator and 1.0 ppm/°C for the case of connecting two compensators to BVR circuit that surpasses the latest published achievements. When expanding the temperature range into the area of low temperatures and using additional compensators in accordance with the specified schematic block diagram, we could expect the reduction of the temperature coefficient to 0.25–0.5 ppm/°C.

References

T. Ghanavati Nejad, E. Farshidi, H. Sjöland, A. Kosarian, “A high precision logarithmic-curvature compensated all CMOS voltage reference,” Analog Integr. Circuits Signal Process., vol. 99, no. 2, pp. 383–392, 2019, doi: https://doi.org/10.1007/s10470-018-1296-0.

S. Jin, Z. Li, J. Li, A. Wang, “A low power bandgap voltage reference with nonlinear voltage curvature compensation,” DEStech Trans. Eng. Technol. Res., no. iceta, 2017, doi: https://doi.org/10.12783/dtetr/iceta2016/7042.

P. L. Schaeffer, “A simple sub-1V voltage reference,” University of Texas at Austin, 2017.

J. F. P. Calvillo, “Design of bandgap voltage reference with curvature compensation for the space industry,” Thesis to obtain the Master of Science Degree in Electronics Engineering, 2016.

H. Wang, J. Wang, J. Su, G. Zhang, F. Liang, “A precision voltage reference circuit with trimming for 16-bit SAR ADC in 55nm CMOS technology,” in 2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM), 2018, pp. 94–97, doi: https://doi.org/10.1109/ICAM.2018.8596484.

R. Madeira, N. Paulino, “Design methodology for an all CMOS bandgap voltage reference circuit,” in 8th Doctoral Conference on Computing, Electrical and Industrial Systems, 2017, pp. 439–446, doi: https://doi.org/10.1007/978-3-319-56077-9_43.

I. Lee, D. Sylvester, D. Blaauw, “A subthreshold voltage reference with scalable output voltage for low-power IoT systems,” IEEE J. Solid-State Circuits, vol. 52, no. 5, pp. 1443–1449, 2017, doi: https://doi.org/10.1109/JSSC.2017.2654326.

Y. Yin, “Performance characteristics and design of voltage references,” Iowa State University, 2017.

N. Bako, I. Broz, Ž. Butković, M. Magerl, A. Barić, “Design of low-power voltage/current references and supply voltage for 9-bit fully differential ADC,” Automatika, vol. 57, no. 1, pp. 239–251, 2016, doi: https://doi.org/10.7305/automatika.2016.03.1616.

E. Barteselli, L. Sant, R. Gaggl, A. Baschirotto, “Design techniques for low-power and low-voltage bandgaps,” Electricity, vol. 2, no. 3, pp. 271–284, 2021, doi: https://doi.org/10.3390/electricity2030016.

L. Peng, X. Jin, M. Liu, “Design and optimization of a low‐noise voltage reference using chopper stabilization technique,” Chinese J. Electron., vol. 26, no. 5, pp. 981–985, 2017, doi: https://doi.org/10.1049/cje.2017.03.020.

A. B. de Andrade, A. Petraglia, C. F. T. Soares, “A constrained optimization approach for accurate and area efficient bandgap reference design,” Microelectron. J., vol. 65, pp. 72–77, 2017, doi: https://doi.org/10.1016/j.mejo.2017.05.012.

H. Huang, Y. Zeng, J. Liao, R. Chen, H. Tan, “Performance optimization for the CMOS voltage reference circuit based on NSGA-II,” in 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018, pp. 82–85, doi: https://doi.org/10.1109/APCCAS.2018.8605700.

K. D. Khalil, N. R. Soliman, H. Omran, “Automation of bandgap voltage reference optimization using vectorized coarse-fine grid search,” in 2019 7th International Japan-Africa Conference on Electronics, Communications, and Computations, (JAC-ECC), 2019, pp. 54–57, doi: https://doi.org/10.1109/JAC-ECC48896.2019.9051334.

K. Murakami et al., “Dynamic optimization of SVR control parameters for improving tap operation efficiency of voltage control in distribution networks,” IEEJ Trans. Electr. Electron. Eng., vol. 16, no. 1, pp. 67–77, 2021, doi: https://doi.org/10.1002/tee.23269.

E. L. Pankratov, “An approach to optimize of manufacturing of a voltage reference based on heterostrucures to increase density of their elements. Analysis of influence of miss-match induced stress and porosity of materials on technological process,” Int. J. Adv. Robot. Expert Syst., vol. 1, no. 2, pp. 41–60, 2022, uri: https://airccse.com/jares/papers/1218jares06.pdf.

S. Meshram, U. Panwar, “Optimization of low power CMOS based voltage reference generator in 32nm,” IJARCCE, vol. 7, no. 8, pp. 47–51, 2018, doi: https://doi.org/10.17148/IJARCCE.2018.7810.

A. V. Borisov, L. N. Pavlov, “Voltage reference modification,” Electron. Commun., no. 4, pp. 14–20, 2013, uri: http://nbuv.gov.ua/UJRN/eisv_2013_4_4.