Output buffer for +3.3 V applications in a 180 nm +1.8 V CMOS technology

Authors

DOI:

https://doi.org/10.3103/S0735272717110061

Keywords:

PCI-X, buffer, level converter, voltage swing, propagation delay, voltage drop, peripheral component interconnect extended

Abstract

A new output buffer realized with low-voltage (+1.8 V) devices to drive high voltage signals for +3.3 V interface, such as peripheral component interconnect extended (PCI-X) applications in a 180 nm CMOS process is proposed in this paper. As PCI-X is a +3.3 V interface, the high voltage gate–oxide stress poses a serious problem to design PCI-X I/O circuits in a 180 nm CMOS process. The performance of the proposed output buffer is examined using Cadence software and the model parameters of a 180 nm CMOS process. The experimental results have hither to confirm that the proposed output buffer can be successfully operated at 100 MHz frequency without suffering high voltage gate–oxide overstress in the +3.3 V interface. A new level converter realized with +1.8 V devices that can convert 0/1 V voltage swing to 0/3.3 V voltage swing is also presented in this paper. The simulation results have confirmed that the proposed level converter can be operated accurately without any voltage drop. The topology, however, reports low sensitivity and has features suitable for VLSI implementation. The proposed circuits are suited for low power design without performance degradation.

Author Biography

Avireni Srinivasulu, JECRC University

Avireni Srinivasulu Was born in Thurimella, Andhra Pradesh, India. He Received the B.Tech Degree from SV University, Tirupati in 1986, ME, Degree from Gulbarga University, Gulbarga in 1991, MS, Degree from Birla Institute of Technology and Science (BITS ), Pilani in 1998 and Ph.D, from Birla Institute of Technology, Mesra, India in 2010. At Present he is working as A Dean (R & D) and Professor of Electronics and Communication Engineering, Vignan's University, Vadlamudi, Guntur, India. He has 25 years of teaching and 15 years of research experience.

Dr. Avireni.S is A Senior Member of IEEE, Senior Member of IACSIT, life Member of ISTE and A Member of the Institution of Engineers (India). He has over 55 Published articles in international journals and international conference proceedings.

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Published

2017-11-30

Issue

Vol. 60 No. 11 (2017)

Section

Research Articles