Efficiency analysis of techniques for weighting elements arrangement on the chip of unary digital-to-analog converter

A. I. Konstantinov; Mikhail S. Yenuchenko; Alexander S. Korotkov

doi:10.3103/S0735272717050041

Authors

A. I. Konstantinov Russian Institute of Radionavigation and Time, St. Petersburg, Russian Federation
Mikhail S. Yenuchenko Peter the Great Saint Petersburg Polytechnic University, Russian Federation https://orcid.org/0000-0002-5301-3871
Alexander S. Korotkov Peter the Great Saint Petersburg Polytechnic University, Russian Federation https://orcid.org/0000-0001-8407-6528

DOI:

https://doi.org/10.3103/S0735272717050041

Keywords:

digital-to-analog converter, unary architecture, systematic error, DAC

Abstract

The paper presents a review of realizations of the matrices of unary DAC weighting elements. A mathematical model of unary DAC taking into account the systematic error has been built. The static characteristics were simulated, and conclusions were made regarding the preferred techniques of forming the matrix of weighting elements for reducing the nonlinearity of unary DACs.

References

MOROZOV, D.V.; YENUCHENKO, M.S. Digital-to-analog converters with unary and segmented architectures. St. Petersburg State Polytechnical University Journal. Computer Science. Telecommunication and Control Systems, n.1, p.81-86, 2013. URL: http://ntv.spbstu.ru/telecom/article/T1.164.2013_13/.

YENUCHENKO, M.S.; MOROZOV, D.V.; PILIPKO, M.M. Eight-bit segmental digital-to-analog converter with enhanced conversion rate. In Problemy razrabotki perspektivnykh mikro- i nanoelektronnykh system 2014. Moscow: IPPM RAN, 2014, Part IV, p.67-70.

YENUCHENKO, M.S. Thermometric decoders for high resolution digital-to-analog converters. Proc. of IEEE NW Russia Young Researchers in Electrical and Electronic Engineering Conf., EIConRusNW, 2–3 Feb. 2016. IEEE, 2016, p.379-384. DOI: https://doi.org/10.1109/EIConRusNW.2016.7448199.

CONG, Y.; GEIGER, R.L. Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays. IEEE Trans. Circuits and Systems II: Analog Digital Signal Processing, v.47, n.7, p.585-595, 2000. DOI: https://doi.org/10.1109/82.850417.

YU, ZHONGIUN; CHEN, DEGANG; GEIGER, RANDY. 1-D and 2-D switching strategies achieving near optimal INL for thermometer-coded current steering DACs. Proc. of 2003 Int. Symp. on Circuits and Systems, ISCAS, 25–28 May 2003. IEEE, 2003, v.1, p.909-912. DOI: https://doi.org/10.1109/ISCAS.2003.1205712.

STARZYK, JANUSZ A.; MOHN, RUSSELL P. Cost-oriented design of a 14-bit current steering DAC macrocell. Proc. of 2003 Int. Symp. on Circuits and Systems, ISCAS, 25–28 May 2003. IEEE, 2003, v.1, p.965-968. DOI: https://doi.org/10.1109/ISCAS.2003.1205726.

LEE, DA-HUEI; KUO, TAI-HAUR; WEN, KOW-LIANG. Low-cost 14-bit current-steering DAC with a randomized thermometer-coding method. IEEE Trans. Circuits and Systems—II: Express Briefs, v.56, n.2, p.137-141, 2009. DOI: https://doi.org/10.1109/TCSII.2008.2011606.

LEE, DA-HUEI; LIN, YU-HONG; KUO, TAI-HAUR. Nyquist-rate current-steering digital-to-analog converters with random multiple data-weighted averaging technique and QN rotated walk switching scheme. IEEE Trans. Circuits And Systems—II: Express Briefs, v.53, n.11, p.1264-1268, 2006. DOI: https://doi.org/10.1109/TCSII.2006.882355.

PALMERS, PIETER; WU, XU; STEYAERT, MICHIEL. A 130 nm CMOS 6-bit full Nyquist 3GS/s DAC. Proc. of IEEE Asian Solid-State Circuits Conf., 12–14 Nov. 2007. IEEE, 2007, p.348-351. DOI: https://doi.org/10.1109/ASSCC.2007.4425702.

ZENG, TAO; CHEN, DEGANG. New sequence switching and layout technique for high-speed high-accuracy current-steering DACs. Proc. of IEEE 2009 National Aerospace & Electronics Conf., NAECON, 21–23 Jul. 2009. IEEE, 2009, p.256-259. DOI: https://doi.org/10.1109/NAECON.2009.5426618.

HUANG, CHUN-YUEH; HOU, TSUNG-TIEN; WANG, HUNG-YU. A 12-bit 250-MHz current-steering DAC. Proc. of 6th Int. Conf. on ASICON, 24–27 Oct. 2005. IEEE, 2005, v.1, p.411-414. DOI: https://doi.org/10.1109/ICASIC.2005.1611348.

VAN DER PLAS, G.A.M.; VANDENBUSSCHE, J.; SANSEN, W.; STEYAERT, M.S.J.; GIELEN, G.G.E. A 14-bit intrinsic accuracy Q/sub 2/ random walk CMOS DAC. IEEE J. Solid-State Circuits, v.34, n.12, p.1708-1718, 1999. DOI: https://doi.org/10.1109/4.808896.

BASTOS, J.; MARQUES, A.M.; STEYAERT, M.S.J.; SANSEN, W. A 12-bit intrinsic accuracy high-speed CMOS DAC. IEEE J. Solid-State Circuits, v.33, n.12, p.1959-1969, 1998. DOI: https://doi.org/10.1109/4.735536.