Power delay optimization of nanoscale 4×1 multiplexer using CMOS based voltage doubler circuit
DOI:
https://doi.org/10.3103/S0735272716110017Keywords:
nano-scale structure, MOS based voltage doubler circuit, leakage power minimization, MOS based low power circuit, sleep transistors MOS configurationAbstract
This paper represents a low leakage, highly efficient and delay improved 4×1 MUX with MOS based voltage doubler circuit cum augmented sleep transistors MOS configuration with nanoscale structure. The unique newly designed voltage doubler circuit is implemented as an additional circuit at the output of the implemented proposed design to step-up the voltage. It means that the output peak voltage is doubled due to the transient of both positive and negative cycles. This stepped-up voltage may be exploited as a stabilized supply for specific applications. The voltage doubler circuit is not enough to improve the overall performance of proposed 4×1 MUX design. In order to integrate the optimization criterion of leakage power and delay performance, the voltage doubler circuit is utilized along with the MOS configuration of augmented sleep transistors. To minimize the parameter of leakage power dissipation the MOS based voltage doubler circuit cum augmented sleep transistors MOS configuration is introduced. This will mitigate the redundant unused leakage power dissipation of the circuit. This additional circuitry brings out the aspired level of output voltage for the proposed and implemented 4×1 MUX with better performance parameters. The whole simulation has been done for the 45 nm technology. It is finally summarized that the leakage power dissipation is minimized up to 55% just around and the delay performance is also improved up to a desired level due to the utilization of MOS based voltage doubler circuit with the MOS configuration of augmented sleep transistors. In this paper, different combinations of MOS based augmented voltage doubler circuit implemented at the output of 4×1 MUX are represented.References
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