Analysis of leakage current and power reduction techniques in FinFET based SRAM cell

Ravindra Singh Kushwah; Vandna Sikarwar

doi:10.3103/S0735272715070031

Authors

Ravindra Singh Kushwah ITM University, India https://orcid.org/0000-0001-5229-0204
Vandna Sikarwar ITM University, India

DOI:

https://doi.org/10.3103/S0735272715070031

Keywords:

FinFET, leakage current, leakage power, static random access memory, SRAM, sub-threshold leakage current, gate leakage current

Abstract

In this paper we have proposed a FinFET based 6T static random access memory (SRAM) cell. FinFET devices can be used to improve the performance, reduce the leakage current and power dissipation. The purpose of this article is to reduce the leakage current and leakage power of FinFET based 6T SRAM cell using various techniques in 45 nm technology. FinFET based 6T SRAM cell has been designed and analysis has been carried out for leakage current and leakage power. For low power memory design the most important problem is to minimize the sub-threshold leakage current and gate leakage current. This work introduces a technique based on threshold voltage, gate oxide thickness and power supply setting together to minimize sub-threshold and gate leakage current of 6T SRAM cell. These simulation results are carried out using Cadence Virtuoso Tool at 45 nm technology.

References

TYAGI, S.; ALAVI, M.; BIGWOOD, R.; BRAMBLETT, T.; BRANDENBURG, J.; CHEN, W.; CREW, B.; HUSSEIN, M.; JACOB, P.; KENYON, C.; LO, C.; MCINTYRE, B.; MA, Z.; MOON, P.; NGUYEN, P.; RUMANER, L.; SCHWEINFURTH, R.; SIVAKUMAR, S.; STETTLER, M.; THOMPSON, S.; TUFTS, B.; XU, J.; YANG, S.; BOHR, M. A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects. Proc. of Int. Tech. Dig. on Electron Devices Meeting, IEDM'00, 10–13 Dec. 2000, San Francisco, CA, USA. IEEE, 2000, p.567-570, DOI: http://dx.doi.org/10.1109/IEDM.2000.904383.

SHUKLA, NEERAJ K.; SINGH, R.K.; PATTANAIK, MANISHA. Design and analysis of a novel low-power SRAM bit-cell structure at deep-sub-micron CMOS technology for mobile multimedia applications. Int. J. Advanced Comput. Sci. Appl., 2011, v.2, n.5, p.43-49, DOI: http://dx.doi.org/10.14569/IJACSA.2011.020507.

AMELIFARD, B.; FALLAH, F.; PEDRAM, M. Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using dual-Vt and dual-Tox assignment. Proc. of IEEE Int. Conf. on Design Automation and Test in Europe, DATE'06, 6–10 March 2006, Munich. IEEE, 2006, v.1, p.1-6, DOI: http://dx.doi.org/10.1109/DATE.2006.243896.

ANAND, P.R.; SEKHAR, P.C. Reduce leakage currents in low power SRAM cell structures. Proc. of Ninth IEEE Int. Symp. on Parallel and Distributed Processing with Applications Workshops, ISPAW, 26–28 May 2011, Busan. IEEE, 2011, p.33-38, DOI: http://dx.doi.org/10.1109/ISPAW.2011.62.

SHUKLA, NEERAJ K.; SINGH, R.K.; PATTANAIK, MANISHA. Analysis of gate leakage current in IP3 SRAM bit-cell under temperature variations in DSM technology. Int. J. Eng. Technol., 2012, v.4, n.1, p.67-71, DOI: http://dx.doi.org/10.7763/IJET.2012.V4.320.

BIRLA, S.; SHUKLA, N.Kr.; MUKHERJEE, D.; SINGH, R.K. Leakage current reduction in 6T single cell SRAM at 90nm technology. Proc. of IEEE Int. Conf. on Advances in Computer Engineering, ACE, 20–21 June 2010, Bangalore, Karnataka, India. IEEE, 2010, p.292-294, DOI: http://dx.doi.org/10.1109/ACE.2010.42.

ZHANG, LI-JUN; WU, CHEN; MA, YA-QI; ZHENG, JIAN-BIN; MAO, LING-FENG. Leakage power reduction techniques of 55 nm SRAM cells. IETE Technical Review, 2011, v.28, n.2, p.315-318.

KANG, S.M.; LEBLEBICI, Y. CMOS digital integrated circuits II. TMH publishing company limited, 2007.

KANDA, K.; SADAAKI, H.; SAKURAI, T. 90% write power-saving SRAM using sense-amplifying memory cell. IEEE J. Solid-State Circuits, Jun. 2004, v.39, n.6, p.927-933, DOI: http://dx.doi.org/10.1109/JSSC.2004.827793.

AGARWAL, A.; LI, H.; ROY K. DRG-cache: a data retention gated-ground cache for low power. Proc. of 39th Int. Conf. on Design Automation, 2002. IEEE, 2002, p.473-478, DOI: http://dx.doi.org/10.1109/DAC.2002.1012671.

AGARWAL, A.; LI, HAI; ROY K. A single-V_t low-leakage gated-ground cache for deep submicron. IEEE J. Solid-State Circuits, Feb. 2003, v.38, n.2, p.319-328, DOI: http://dx.doi.org/10.1109/JSSC.2002.807414.

JOHRI, RAJ; KUSHWAH, RAVINDRA SINGH; SINGH, RAGHVENDRA; AKASHE, SHYAM. Modeling and simulation of high speed 8T SRAM cell. Proc. of Seventh Int. Conf. on Bio-Inspired Computing: Theories and Applications. Advances in Intelligent Systems and Computing, BIC-TA, 2012. 2013, v.2, p.245-251, DOI: http://dx.doi.org/10.1007/978-81-322-1041-2_21.

SHEIKH, FARHANA; VARADARAJAN, VIDYA. The impact of device-width quantization on digital circuit design using FinFET structures. Proc. EE241 Spring, 2004, p.1-6.

QIN, HULFANG; CAO, YU; MARKOVIC, D.; VLADIMIRESCU, A.; RABAEY J. SRAM leakage suppression by minimizing standby supply voltage. Proc. of IEEE Int. Symp. on Quality Electronic Design, 2004. IEEE, 2004, p.55-60, DOI: http://dx.doi.org/10.1109/ISQED.2004.1283650.