Inter-modulation linearity investigation of an optimally designed and optimally biased LNA for wireless LAN

Indra Vijay Singh; Muhmmad Shah Alam

doi:10.3103/S0735272715050015

Authors

Indra Vijay Singh Aligarh Muslim University, India
Muhmmad Shah Alam Aligarh Muslim University, India

DOI:

https://doi.org/10.3103/S0735272715050015

Keywords:

non-linear circuit, double gate, SOI, low noise amplifier, LNA, low power

Abstract

This paper presents the effects of process parameters variations of new underlap SOI MOSFETs (underlap SOI technology with spacer covered) on linearity investigation of cascode low noise amplifier (LNA) for wireless LAN application. By quantifying the linearity of the LNA in-terms of third order intercept (IP3), the paper presents guidelines for optimum value of spacer s, film thickness T_Si doping gradient d and gate length L_G of the underlap device for linearity enhancement of the LNA. Based on a new Figure-of-Merit of LNA (FoM_LNA) involving available signal power gain G, IP3, noise figure (NF) and dc power consumption P_dc, it has been found that FoM_LNA in double gate (DG) configuration is much higher than single gate (SG) at the optimum gate overdrive V_OD = 75 mV. This is due to a combined effect of higher value of G and IP3 in the DG configuration. By comparing with limited available experimental data of 0.18 µm bulk technology, it has been found that using new underlap SOI MOSFETs with gate length, L_G = 60 nm (effective gate length L_eff = 92 nm) optimally designed and optimally biased LNA gives almost two times improvement in the proposed FoM_LNA. With optimal bias the LNA achieved as NF ~ 2.27 dB, IP3 ~ +7.75 dBm, G ~ 20.86 dB and consumed power equal to 2.5 mW.

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