Analysis of leakage reduction technique on FinFET based 7T and 8T SRAM cells

Ravindra Singh Kushwah; Shyam Akashe

doi:10.3103/S0735272714090015

Authors

Ravindra Singh Kushwah ITM University, India https://orcid.org/0000-0001-5229-0204
Shyam Akashe ITM University, Gwalior, India

DOI:

https://doi.org/10.3103/S0735272714090015

Keywords:

FinFET, leakage current, leakage power, static random access memory, SRAM, self-controllable voltage level, SVL, upper SVL, lower SVL

Abstract

We propose a FinFET based 7T and 8T Static Random Access Memory (SRAM) cells. FinFETs also promise to improve challenging performance versus power tradeoffs. Designers can run the transistors more rapidly and use the similar amount of power, compared to the planar CMOS, or run them at the similar performance using less power. The aim of this paper is to reduce the leakage current and leakage power of FinFET based SRAM cells using Self-controllable Voltage Level (SVL) circuit Techniques in 45nm Technology. SVL circuit allows supply voltage for a maximum DC voltage to be applied on active load or can reduce the supplied DC voltage to a load in standby mode. This SVL circuit can reduce standby leakage power of SRAM cell with minimum problem in terms of chip area and speed. High leakage currents in submicron regimes are primary contributors to total power dissipation of bulk CMOS circuits as the threshold voltage V_th, channel length L and gate oxide thickness t_ox are scaled down. The leakage current in the SRAM cell increases due to reduction in channel length of the MOSFET. Two methods are used; one method in which the supply voltage is reduced and other method in which the ground potential is increased. The Proposed FinFET based 7T and 8T SRAM cells have been designed using Cadence Virtuoso Tool, all the simulation results has been generated by Cadence SPECTRE simulator at 45nm technology.

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