Design and optimization of flash type analog to digital converter using augmented sleep transistors with current mode logic
DOI:
https://doi.org/10.3103/S0735272713100026Keywords:
leakage power, ASTCML logic, Flash type analog to digital converter, ADCAbstract
This paper represents the low leakage & the delay performance optimization of Flash type Analog to Digital converter using Augmented Sleep Transistors with Current Mode Logic (ASTCML) at 45 nm technology. It is realized that the leakage power is reduced 50% approximately in ASTCML logic based analog to digital converter design at 1 V supply voltage. Due to reduced leakage power, the probability of causing thermal runaway is decreased and the design stagnation is increased. Even though the featured analog to digital converter is designed using combination of PMOS and NMOS. The anticipated analog to digital converter is appropriate for high speed and wireless network application. In this paper, different consecutive designs with flash type analog to digital converter are represented.
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