Accurate modeling of nanoscale gate underlap SOI MOSFET and design of low noise amplifier for RF applications

Indra Vijay Singh; Muhmmad Shah Alam; G. A. Armstrong

doi:10.3103/S0735272713060010

Authors

Indra Vijay Singh Aligarh Muslim University, India
Muhmmad Shah Alam Aligarh Muslim University, India
G. A. Armstrong Queen’s University Belfast, United Kingdom

DOI:

https://doi.org/10.3103/S0735272713060010

Keywords:

gate underlap, non-quasi-static, silicon-on-insulator, low noise amplifier, low power

Abstract

Paper presents an accurate model by accounting non-quasi-static and extrinsic parasitic effects for 90 nm gate underlap SOI MOSFETs for RF applications. Generated Y-parameters from the model up to 20 GHz matched very well with 2D ATLAS (with an average error of ~5%), whereas results from quasi-static predictive technology model differ significantly (>20%). Calculated transit frequency f_T and maximum frequency of oscillation f_max have been found as ~108 and ~130 GHz respectively. Simulated noise figure at drain-to-source current I_DS ≈ 0.64 mA and drain-to-source voltage V_DS = 1 V was found to be ≈2.8 dB with gate resistance R_ge = 3 Ω. A low noise amplifier (LNA) designed at operating frequency of 5.8 GHz using the model has shown good match at input (S₁₁ ≈ –15 dB), output (S₂₂ ≈ –16 dB) and gain (S₂₁ ≈ 15 dB). A new figure-of-merit of LNA (FoM_LNA) involving signal power gain G, noise factor F and dc power consumption P_dc has been proposed. By comparing with limited available measured data of 180 nm bulk, it has been found that underlap LNA (simulated using the developed model) gives almost three times improvement in the proposed FoM_LNA.

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