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Simulation results of selected techniques for combined error functions and for 6-bit DAC

Efficiency analysis of techniques for weighting elements arrangement on the chip of unary digital-to-analog converter

A. I. Konstantinov, M. S. Yenuchenko, Alexander S. Korotkov


The paper presents a review of realizations of the matrices of unary DAC weighting elements. A mathematical model of unary DAC taking into account the systematic error has been built. The static characteristics were simulated, and conclusions were made regarding the preferred techniques of forming the matrix of weighting elements for reducing the nonlinearity of unary DACs.


digital-to-analog converter; unary architecture; systematic error; DAC

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