Designs of multi-bit sigma delta modulator




analog to digital converter, sigma delta modulator, noise shaping, MASH, signal to noise plus distortion ratio, oversampling ratio


This paper presents new design variants of third order multi-bit sigma delta modulator (SDM): low distortion SDM and cascaded SDM. The proposed modulator based on the conventional SDM such L-0 MASH (Multi-stAge noise SHaping) and interstage feedback topology. The MASH SDM is not a single loop system. One of the drawback is that performance is limited by uncancelled noise from the first modulator and interstage feedback topology only cancels nonlinear errors introducing by multi-bit DAC in the final stage, but the rest stage still contains DAC nonlinearity errors without any noise shaping which still degrade overall system performance. An improved version of cascaded multi-bit SDM is proposed to overcome these problems mentioned above. In addition a third order low distortion SDM is also proposed. Simulation results verify the superiority of the both proposed modulator.


SCHREIER, R. An empirical study of high-order single-bit delta-sigma modulators. IEEE Trans. Circuits Syst. II: Analog Digital Signal Process., Aug. 1993, v.40, n.8, p.461-466, DOI:

NORSWORTHY, STEVEN R.; SCHREIER, RICHARD; TEMES, GABOR C. (eds.). Delta-Sigma Converters: Theory, Design and Simulation. IEEE Press, 1997.

LONGO, L.; COPELAND, M. A 13 bit ISDN-band oversampled ADC using two-stage third order noise shaping. Proc. of IEEE Conf. on Custom Integrated Circuits, Jan. 1988, Rochester, NY. IEEE, 1988, p.21.2/1-21.2/4, DOI:

RIBNER, D.B. A comparison of modulator networks for high-order oversampled SD analog-to-digital converters. IEEE Trans. Circuits Syst., Feb. 1991, v.38, n.2, p.145-159, DOI:

WILLIAMS III, L.A.; WOLLEY, B.A. Third-order cascaded sigma-delta modulators. IEEE Trans. Circuits Syst., May 1991, v.38, n.5, p.489-498, DOI:

SILVA, J.; MOON, U.; STEENSGAARD, J.; TEMES, G.C. Wideband low-distortion delta-sigma ADC topology. IET Electron. Lett., Jun. 2001, v.37, n.12, p.737-738, DOI:

CHIANG, JEN-SHIUN; CHANG, TENG-HUNG; CHOU, POU-CHU. Novel noise shaping of cascaded sigma-delta modulator for wide bandwidth applications. Proc. of 8th IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS, 2001. IEEE, 2001, v.3, p.1379-1382, DOI:

LESLIE, T.C.; SINGH, B. An improved sigma-delta modulator architecture. Proc. of IEEE Int. Symp. on Circuits and Systems, 1-3 May 1990, New Orleans, LA. IEEE, 1990, v.1, p.372-375, DOI:

HAIRAPETIAN, A.; TEMES, G.C.; ZHANG, Z.X. Multibit sigma delta modulator with reduced sensitivity to DAC nonlinearity. Electron. Lett., May 1991, v.27, n.11, p.990-991, DOI:

KUO, TAI-HAUR; CHEN, KUAN-DAR; YENG, HORNG-RU. A wideband CMOS sigma-delta modulator with incremental data weighted averaging. IEEE J. Solid-State Circuits, Jan. 2002, v.37, n.1, p.11-17, DOI:

SCHREIER, RICHARD. The Delta-Sigma Toolbox,, File Exchange > Control and System Modeling > Control Design > delsig.

MATSUYA, Y.; UCHIMURA, K.; IWATA, ATSUSHI; KOBAYASHI, T.; ISHIKAWA, M.; YOSHITOME, T. A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping. IEEE J. Solid-State Circuits, Dec. 1987, v.22, n.6, p.921-929, DOI:

HAIRAPETIAN, A.; TEMES, G.C. A dual-quantization multi-bit sigma delta analog/digital converter. Proc. of IEEE Int. Symp. on Circuits and Systems, ISCAS’94, 30 May-2 Jun. 1994, London. IEEE, 1994, v.5, p.437-440, DOI:

CHIANG, JEN-SHIUN; CHANG, TENG-HUNG; CHOU, POU-CHU. A novel wideband low-distortion cascaded sigma-delta ADC. Proc. of IEEE Int. Symp. on Circuits and Systems, ISCAS, 26–29 May 2002, Phoenix-Scottsdale, AZ. IEEE, 2002, v.2, p.636-639, DOI:

WANG, Q.-Q.; GE, B.-J.; FENG, X.-X.; WANG, X.-A. Digital noise shaping multibit delta-sigma modulator. Electron. Lett., Aug. 2010, v.46, n.16, p.1110-1111, DOI:





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