DOI: https://doi.org/10.3103/S073527271603002X



Development of 3T eDRAM gain cells for enhancing read margin and data retention
Abstract
Keywords
References
SZE, S.M. Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.
MATICK, R.E.; SCHUSTER, S.E. Logic-based eDRAM: Origins and rationale for use. IBM J. Res. Develop., Jan. 2005, v.49, n.1, p.145-165, DOI: http://dx.doi.org/10.1147/rd.491.0145.
BARTH, J.; REOHR, W.R.; PARRIES, P.; FREDEMAN, G.; GOLZ, J.; SCHUSTER, S.E.; MATICK, RICHARD E.; HUNTER, H.; TANNER, C.C.; HARIG, J.; KIM, H.; KHAN, B.A.; GRIESEMER, J.; HAVRELUK, R.P.; YANAGISAWA, K.; KIRIHATA, T.; IYER, S.S. A 500 MHz random cycle, 1.5 ns latency, SOI embedded DRAM macro featuring a three-transistor micro sense amplifier. IEEE J. Solid-State Circuits, Jan. 2008, v.43, n.1, p.86-95, DOI: http://dx.doi.org/10.1109/JSSC.2007.908006.
LUK, W.K.; CAI, JIN; DENNARD, R.H.; IMMEDIATO, M.J.; KOSONOCKY, S.V. A 3-transistor DRAM cell with gated diode for enhanced speed and retention time. Proc. of IEEE Symp. on VLSI Circuits, Honolulu, HI : Digest of Technical Papers. IEEE, 2006, p.184-185, DOI: http://dx.doi.org/10.1109/VLSIC.2006.1705371.
CHUN, KI CHUL; JAIN, P.; LEE, JUNG HWA; KIM, C.H. A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias. Proc. of IEEE Symp. on VLSI Circuits, 16-18 June 2009, Kyoto, Japan. IEEE, 2009, p.134-135, http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5205419&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5205419.
KIYOO ITOH, B.S. Trends in megabit DRAM circuit design. IEEE J. Solid-State Circuits, Jun. 1990, v.25, n.3, p.778-789, DOI: http://dx.doi.org/10.1109/4.102676.
AKASHE, SHYAM; SINHA, DEEPAK KUMAR; SHARMA, SANJAY. A low leakage current power 45-nm CMOS SRAM. Indian J. Sci. Technol., 2011, v.4, n.4, p.440-442, DOI: http://dx.doi.org/10.17485/ijst/2011/v4i4/30019.
SHRIVASTAVA, AKANSHA; KHANDELWAL, SAURABH; AKASHE, SHYAM. Low power analysis in single stage source coupled VCO with AVL technique using nanoscale CMOS technology. Proc. of IEEE Students Conf. on Engineering and Systems, SCES, 12-14 Apr. 2013, Allahabad, India. IEEE, 2013, p.1–6, DOI: http://dx.doi.org/10.1109/SCES.2013.6547488.
CHANDRAKASAN, A.P.; BRODERSEN, R.W. Low Power Digital CMOS Design. Wiley–IEEE Press, Jan. 1998.
BUTTS, J.A.; SOHI, G.S. A static power model for architects. Proc. of 33rd Annual IEEE/ACM Int. Symp. on Microarchitecture, MICRO-33, 10-13 Dec. 2000, Monterey, CA. IEEE, 2000, p.191-201, DOI: http://dx.doi.org/10.1109/MICRO.2000.898070.
SEEVINCK, E.; VAN BEERS, P.J.; ONTROP, H. Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM’s. IEEE J. Solid-State Circuits, Apr. 1991, v.26, n.4, p.525-536, DOI: http://dx.doi.org/10.1109/4.75050.
SIM, JAE-YOON; YOON, HONGIL; CHUN, KI-CHUL; LEE, HYUN-SEOK; HONG, SANG-PYO; LEE, KYU-CHAN; YOO, JEI-HWAN; SEO, DONG-IL; CHO, SOO-IN. A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor. IEEE J. Solid-State Circuits, Apr. 2003, v.38, n.4, p.631-640, DOI: http://dx.doi.org/10.1109/JSSC.2003.809514.
When you copy an active link to the material is required
ISSN 1934-8061 (Online), ISSN 0735-2727 (Print)
tel./fax +38044 204-82-31, 204-90-41