DOI: https://doi.org/10.3103/S0735272715050015
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2D structure of new underlap engineered SOI MOSFET

Inter-modulation linearity investigation of an optimally designed and optimally biased LNA for wireless LAN

Indra Vijay Singh, Muhmmad Shah Alam

Abstract


This paper presents the effects of process parameters variations of new underlap SOI MOSFETs (underlap SOI technology with spacer covered) on linearity investigation of cascode low noise amplifier (LNA) for wireless LAN application. By quantifying the linearity of the LNA in-terms of third order intercept (IP3), the paper presents guidelines for optimum value of spacer s, film thickness TSi doping gradient d and gate length LG of the underlap device for linearity enhancement of the LNA. Based on a new Figure-of-Merit of LNA (FoMLNA) involving available signal power gain G, IP3, noise figure (NF) and dc power consumption Pdc, it has been found that FoMLNA in double gate (DG) configuration is much higher than single gate (SG) at the optimum gate overdrive VOD = 75 mV. This is due to a combined effect of higher value of G and IP3 in the DG configuration. By comparing with limited available experimental data of 0.18 µm bulk technology, it has been found that using new underlap SOI MOSFETs with gate length, LG = 60 nm (effective gate length Leff = 92 nm) optimally designed and optimally biased LNA gives almost two times improvement in the proposed FoMLNA. With optimal bias the LNA achieved as NF ~ 2.27 dB, IP3 ~ +7.75 dBm, G ~ 20.86 dB and consumed power equal to 2.5 mW.


Keywords


non-linear circuit; double gate; SOI; low noise amplifier; LNA; low power

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References


LIU, REN-CHIEH; LEE, CHUNG-RUNG; WANG, HUEI; WANG, CHORNG-KUANG. A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-μm CMOS technology. Proc. of IEEE Symp. on Radio Frequency Integrated Circuits, RFIC, 3–4 June 2002, Seattle, WA, USA. IEEE, 2002, p.221-224, DOI: http://dx.doi.org/10.1109/RFIC.2002.1012036.

ZHANG, HENG; SANCHEZ-SINENCIO, EDGAR. Linearization Techniques for CMOS low noise amplifiers: A tutorial. IEEE Trans. Circuits Syst. I: Regular Papers, Jan. 2011, v.58, n.1, p.22-36, DOI: http://dx.doi.org/10.1109/TCSI.2010.2055353.

GHOSH, DIPANKAR; PARIHAR, MUKTA SINGH; ARMSTRONG, G. ALASTAIR; KRANTI, ABHINAV. Optimally designed moderately inverted double gate SOI MOSFETs for low-power RFICs. Semicond. Sci. Tech., 2012, v.27, n.12, p.125004, DOI: http://dx.doi.org/10.1088/0268-1242/27/12/125004.

PARK, SUNGKYUNG; KIM, WONCHAN. Design of a 1.8 GHz low-noise amplifier for RF front-end in 0.8 μm CMOS technology. IEEE Trans. Cons. Electron., Feb. 2001, v.47, n.1, p.10-15, DOI: http://dx.doi.org/10.1109/30.920413.

KAYA, SAVAS; MA, WEI. Optimization of RF linearity in DG-MOSFETs. IEEE Electron Device Lett., May 2004, v.25, n.5, p.308-310, DOI: http://dx.doi.org/10.1109/LED.2004.826539.

KRANTI, ABHINAV; ARMSTRONG, G.A. Nonclassical channel design in MOSFETs for improving OTA gain-bandwidth trade-off. IEEE Trans. Circuits Syst. I: Regular Papers, Dec. 2010, v.57, n.12, p.3048-3054, DOI: http://dx.doi.org/10.1109/TCSI.2010.2071470.

LEE, TZUNG-YIN; CHENG, YUHUA. High frequency characterization and modelling of distortion behaviour of MOSFETs for RF IC design. IEEE J. Solid-State Circuits, Sept. 2004, v.39, n.9, p.1407-1414, DOI: http://dx.doi.org/10.1109/JSSC.2004.829376.

KRANTI, ABHINAV; CHUNG, TSUNG MING; RASKIN, JEAN-PIERRE. Gate length scaling and microwave performance of double gate nanotransistors. Int. J. Nanosci., Dec. 2005, v.4, n.5-6, p.1021-1024, DOI: http://dx.doi.org/10.1142/S0219581X05004005.

RAZAVI, B. RF Micro-Electronics. Prentice-Hall, 1998.

TIEMEIJER, L.F.; VAN LANGEVELDE, R.; GAILLARD, O.; HAVENS, R.J.; BALTUS, P.G.M.; WOERLEE, P.H.; KLAASSEN, D.B.M. RF distortion characterisation of sub-micron CMOS. Proc. of 30th European Conf. on Solid-State Device Research, 11–13 Sept. 2000. IEEE, 2000, p.464-467, DOI: http://dx.doi.org/10.1109/ESSDERC.2000.194815.

ALAM, M.S.; KRANTI, A.; ARMSTRONG, G.A. Investigation of gate underlap design on linearity of operational transconductance amplifier. Proc. of World Congress on Engineering and Computer Science, WCECS 2010, October 20–22, 2010, San Francisco, USA. IEEE, 2010, v.2.

MA, MING-WEN; WU, CHIEN-HUNG; YANG, TSUNG-YU; KAO, KUO-HSING; WU, WOEI-CHERNG; WANG, SHUI-JINN; CHAO, TIEN-SHENG; LEI, TAN-FU. Impact of high-κ offset spacer in 65-nm node SOI devices. IEEE Electron Device Lett., Mar. 2007, v.28, n.3, p.238-241, DOI: http://dx.doi.org/10.1109/LED.2007.891282.

CERDEIRA, A.; ALEMAN, M.; KILCHITSKA, V.; COLLAERT, N.; DE MEYER, K.; FLANDRE, D. Non-linearity analysis of FinFETs. Proc. of 6th Int. Caribbean Conf. on Devices, Circuits and Systems, 26–28 April 2006, Playa del Carmen. IEEE, 2006. — P. 9–12. — DOI : http://dx.doi.org/10.1109/ICCDCS.2006.250827.

PARK, JONG-TAE; COLINGE, JEAN-PIERRE. Multiple-gate SOI MOSFETs: device design guidelines. IEEE Trans. Electron Devices, Dec. 2002, v.49, n.12, p.2222-2229, DOI: http://dx.doi.org/10.1109/TED.2002.805634.

International Technology Roadmap for Semiconductors. 2011 edition.

Silvaco ATLAS-2011, www.silvaco.com.

WONG, HIU YUNG; SHIN, KYOUNGSUB; CHAN, M. The gate misalignment effects of the sub-threshold characteristics of sub-100 nm DG-MOSFETs. Proc. of IEEE Hong Kong Meeting on Electron Device Meeting, 2002. IEEE, 2002, p.91-94, DOI: http://dx.doi.org/10.1109/HKEDM.2002.1029164.

Advanced Design System (ADS) 2012, www.agilent.com.

LEE, T.H. The Design of CMOS Radio-Frequency Integrated Circuits. UK Cambridge University Press, 1998.

ARORA, RAJAN; CRESSLER, JOHN D. Operating voltage constraints in 45-nm SOI nMOSFETs and cascode cores. IEEE Trans. Electron Devices, Jan. 2013, v.60, n.1, p.132-139, DOI: http://dx.doi.org/10.1109/TED.2012.2227967.

WANG, Y.S.; LU, L.-H. 5.7 GHz low-power variable-gain LNA in 0.18 µm CMOS. Electron. Lett., 20 Jan. 2005, v.41, n.2, p.66-68, DOI: http://dx.doi.org/10.1049/el:20057230.

KWON, ICKJIN; LEE, KWYRO. An accurate behavioral model for RF MOSFET linearity analysis. IEEE Microwave Wireless Compon. Lett., Dec. 2007, v.17, n.12, p.897-899, DOI: http://dx.doi.org/10.1109/LMWC.2007.910518.

BAKI, ROLA A.; TSANG, TOMMY K.K.; EL-GAMAL, MOURAD N. Distortion in RF CMOS short-channel low-noise amplifiers. IEEE Trans. Microwave Theory Tech., Jan. 2006, v.54, n.1, p.46-56, DOI: http://dx.doi.org/10.1109/TMTT.2005.860897.

PEDRO, JOSE CARLOS; CARVALHO, NUNO BORGES. Intermodulation Distortion in Microwave and Wireless Circuits. Artech House, Inc., 2003, 450 p.

LUYKEN, R.J.; SCHULZ, T.; HARTWICH, J.; DREESKORNFELD, L.; STADELE, M.; ROSNER, W. Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime. Solid-State Electron., July 2003, v.47, n.7, p.1199-1203, DOI: http://dx.doi.org/10.1016/S0038-1101(03)00038-8.

KANG, SANGHOON; CHOI, BYOUNGGI; KIM, BUMMAN. Linearity analysis of CMOS for RF application. IEEE Trans. Microwave Theory Tech., Mar. 2003, v.51, n.3, p.972-977, DOI: http://dx.doi.org/10.1109/TMTT.2003.808709.

TOOLE, B.; PLETT, C.; CLOUTIER, M. RF circuit implications of moderate inversion enhanced linear region in MOSFETs. IEEE Trans. Circuits Syst. I: Regular Papers, Feb. 2004, v.51, n.2, p.319-328, DOI: http://dx.doi.org/10.1109/TCSI.2003.822400.

SONG, ICKHYUN; JEON, JONGWOOK; JHON, HEE-SAUK; KIM, JUNSOO; PARK, BYUNG-GOOK; LEE, JONG DUK; SHIN, HYUNGCHEOL. A simple figure of merit of RF MOSFET for low noise amplifier design. IEEE Electron Device Lett., Dec. 2008, v.29, n.12, p.1380-1382, DOI: http://dx.doi.org/10.1109/LED.2008.2006863.

IBRAHIM, ABU BAKAR; OTHMAN, ABDUL RANI; HUSSAIN, MOHD NOR; JOHAL, MOHAMMAD SYAHRIR. High gain, low noise cascode LNA with RF amplifier at 5.8 GHz using T-matching networks. Proc. of 2nd Int. Conf. on Advancements in Electronics and Power Engineering, ICAEPE’2012, June 30–July, 2012, Bali, http://www.academia.edu/3121327/high_gain_low_noise_cascode_LNA_with_RF_amplifier_at_5.8GHz_using_T-matching_network.

SHI, JINGLIN; XIONG, YONG ZHONG; KANG, KAI; NAN, LAN; LIN, FUJIANG. RF noise of 65-nm MOSFETs in the weak-to-moderate-inversion region. IEEE Electron Device Lett., Feb. 2009, v.30, n.2, p.185-188, DOI: http://dx.doi.org/10.1109/LED.2008.2010464.

SCHOLTEN, ANDRIES J.; TIEMEIJER, LUUK F.; VAN LANGEVELDE, RONALD; HAVENS, RAMON J.; ZEGERS-VAN DUIJNHOVEN, ADRIE T.A.; VENEZIA, VINCENT C. Noise modeling for RF CMOS circuit simulation. IEEE Trans. Electron Devices, Mar. 2003, v.50, n.3, p.218-232, DOI: http://dx.doi.org/10.1109/TED.2003.810480.







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