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2D structure of new underlap engineered SOI MOSFET

Inter-modulation linearity investigation of an optimally designed and optimally biased LNA for wireless LAN

Indra Vijay Singh, Muhmmad Shah Alam


This paper presents the effects of process parameters variations of new underlap SOI MOSFETs (underlap SOI technology with spacer covered) on linearity investigation of cascode low noise amplifier (LNA) for wireless LAN application. By quantifying the linearity of the LNA in-terms of third order intercept (IP3), the paper presents guidelines for optimum value of spacer s, film thickness TSi doping gradient d and gate length LG of the underlap device for linearity enhancement of the LNA. Based on a new Figure-of-Merit of LNA (FoMLNA) involving available signal power gain G, IP3, noise figure (NF) and dc power consumption Pdc, it has been found that FoMLNA in double gate (DG) configuration is much higher than single gate (SG) at the optimum gate overdrive VOD = 75 mV. This is due to a combined effect of higher value of G and IP3 in the DG configuration. By comparing with limited available experimental data of 0.18 µm bulk technology, it has been found that using new underlap SOI MOSFETs with gate length, LG = 60 nm (effective gate length Leff = 92 nm) optimally designed and optimally biased LNA gives almost two times improvement in the proposed FoMLNA. With optimal bias the LNA achieved as NF ~ 2.27 dB, IP3 ~ +7.75 dBm, G ~ 20.86 dB and consumed power equal to 2.5 mW.


non-linear circuit; double gate; SOI; low noise amplifier; LNA; low power

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