Algorithms of coding the internal states of finite-state machine focused on the reduced power consumption
New algorithms of coding the internal states of finite-state machine (FSM) have been (were) proposed. These algorithms make it possible to reduce the power consumption of sequential devices at the stage of their designing. The algorithms presented are based on solving the minimization problem of the switching activity of FSM memory elements that directly results in the reduced power consumption. The sequential and iterative algorithms of coding the FSM internal states have been proposed that are focused on the input power reduction. The experimental studies corroborated a substantial reduction of the power consumption in devices designed with the use of the described algorithms of coding as compared with the known approaches.
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