Efficient fused MAC unit using multi-operand parallel prefix adder





In this brief, various multi-operand parallel prefix adders are designed and they are implemented in fused multiply-accumulate (MAC) unit. A multi-operand adder is the fascinating technique in contrast with a network of 2-operand adders in many arithmetic applications. Also, the parallel prefix adder is one of the high speed adders. Thus, multi-operand adders are designed using various parallel prefix graphs which are used for implementing fused MAC unit. Initially, the parallel prefix adders are structured and analyzed. Secondly, the designed parallel prefix adders are restructured for multi-operand operations. Finally, MAC unit is implemented using various multi-operand adders. The proposed multi-operand parallel prefix adders are designed in Xilinx Kintex 7 FPGA. In contrast with existing one, the Ladner Fischer multi-operand adder provides optimum results based on the power consumption, area and delay. In accordance with the results attained from Kintex 7 FPGA, the Ladner Fischer multi-operand adder outperforms based on power consumption by 38.06%, path delay by 17.54% and number of LUTs by 26.55% against the existing one. Subsequently, the Fused MAC unit designed using Ladner Fischer multi-operand adder provides the reduction in power consumption by 39.95%, path delay by 16.83% and number of LUTs by 13.73% in contrast with the classical MAC unit.


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Prefix diagram of KSA





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